The error “Top-level module ‘and3’ is undefined” is mostly caused by project configuration or naming inconsistencies. Troubleshoot as follows:
Check whether the file exists: Confirm that and3.v (for Verilog) or and3.bdf (for schematic) appears under Files in the Project Navigator. If not, create the file first, starting with `module and3 (…)`.
Check whether the file is added to the project: An error also occurs if the file exists but has not been added. Right‑click the file and select Add to Project (or go to Project → Add File), then verify it shows up in the project file list.
Check for consistent module names: The code must declare `module and3 (…)`. Common pitfalls include names such as and3_gate, And3 (Quartus is case‑sensitive), or mismatched port declarations.
Set as top‑level entity: Right‑click the file or entity in Project Navigator and choose Set as Top‑Level Entity. For schematic designs, ensure the .bdf file is set as the top level and has been compiled to generate its symbol.
Run a full recompilation: Select Processing → Start Compilation (or press Ctrl+L), and confirm there are no other undefined dependencies.
If multiple source files are used, check whether and3 is indirectly referenced by another top‑level entity and causing conflicts. Clean and rebuild the project if necessary.